The low breakdown voltage of transistors is problematic for power applications. High frequency transistors such as but not limited to submicron CMOS transistors, silicon on insulator (CMOS-SOI) transistors, silicon (Si) transistors, silicon germanium (SiGe) transistors, and SiGe heterojunction bipolar transistors (HBT) support maximum voltages ranging from ten volts to four volts or even lower between the drain to source, drain to gate, collector to emitter, or collector to base. Nevertheless, certain applications demand the use of a high voltage supply resulting in operating conditions above what these devices can support. Applications requiring a high power output to a high impedance load and other applications cannot be implemented if low breakdown voltage transistors are used in a conventional way.
Cascode topology is one way to increase the operating voltage for transistors. A conventional cascode topology can include, for example, two transistors connected in series with the source of a first MOSFET transistor connected to the drain of a second MOSFET transistor, or the emitter of a first bipolar junction transistor (BJT) coupled to the collector of a second bipolar junction transistor.
A conventional cascode arrangement with two transistors connected in series presents several limitations. First, the maximum voltage allowable between the collector to emitter or the drain to source is limited to twice the voltage that an individual transistor can support. Higher voltage cannot be applied without risking voltage breakdown.
Second, if the gate or base voltage of the second transistor is held constant, a DC voltage between the collector and the base or the base and the emitter of a BJT, or between the drain and the gate or the gate and the source of a FET transistor, can cause a voltage breakdown.
Furthermore, in applications using integrated circuits, a large bypass capacitor is required to keep the voltage at the gates or bases constant. This capacitor will occupy an undesired large area increasing the cost of the integrated circuit and making the layout of the circuit more difficult.
These limitations restrict the use of conventional cascode topologies to the applications that require an output voltage lower than twice the breakdown voltage of the individual transistor.